1. Field of the Invention
The invention relates in general to a planarization process of chemical mechanical polishing (CMP), and more particularly to a planarization process of depositing materials with various polishing rates to achieve the best planarization.
2. Description of the Related Art
Surface planarization is an important technique dealing with high density photolithography in the field of semiconductor processes. A smooth surface having no relief can avoid scattering during exposure and achieve accurate pattern transfer. Planarization techniques comprise spin-on glass (SOG) and chemical mechanical polishing (CMP). The requirements for flatness of the sub-half-micro technique in semiconductor fabrication cannot be met by SOG. CMP is the only technique able to provide global planarization on the very large scale integration (VLSI) even on the ultra large scale integration (ULSI).
Basically, CMP uses the principle of mechanical polishing and an apposite chemical promoter to polish a bumpy surface. FIG. 1A is a top view of a conventional apparatus for chemical mechanical polishing. FIG. 1B is a cross-sectional view of the conventional apparatus for chemical mechanical polishing. The conventional apparatus for chemical mechanical polishing comprises a polishing table 10, a holder 11 which is used to hold a chip 12, a polishing pad 13 on the polishing table 10, a service pipe 14 which is used to transport slurry 19 to the polishing pad 13 and a pump 15 which is used to carry a slurry 19 into the service pipe 14. The polishing table 10 and the holder 11 rotate variously along particular directions 18a and 18b as shown in FIG. 1A and FIG. 1B. The holder 11 holds the back 16 of the chip 12 and puts the front 17 of the chip 12 on the polishing pad 13. The service pipe 14 continually transports the slurry 19 distilled from the pump 15 to the polishing pad 13. The process of chemical mechanical polishing uses a chemical promoter from the slurry 19 to make a chemical reaction on the front 17 of the chip 12. The chemical reaction forms a polishing layer that is easy polished. Then, while the chip 12 sits on the polishing pad 13, mechanical polishing is performed on the chip 12 to remove the overhang of the easily polished polishing layer, using abrasive particles in the slurry 19. A planar surface is formed by repeating the chemical reactive step and the mechanical polishing step. FIG. 1c and FIG. 1D are cross-sectional views of the conventional process of chemical mechanical polishing as used to form a dielectric layer on a conductor section. Referring to FIG. 1C, a semiconductor substrate 110 has a conductive section 120. A thick dielectric layer 130 is deposited on the semiconductor substrate 110. Deposition of the thick dielectric layer 130 creates a difference in height between region 131, located above the conductive region 120, and region 132, located above the semiconductor 110. This results in a step between region 131 and region 132. The material of the thick dielectric layer 130 is, for example, silicon dioxide. A metal CMP step is performed to polish the thick dielectric layer 130. Theoretically, the region 131 above the conductive section 120 and the region 132 above the semiconductor substrate 110 are polished to a flat surface. However, since the high section of the step and the low section of the step both suffer chemical etching by the slurry, the surface of the dielectric layer 130 is uneven as shown in FIG. 1D.